1. Field of the Invention
The present invention relates generally to sample-and-hold circuits used to temporarily store analog voltages, and more particularly, to a sample-and-hold circuit that is less susceptible to voltage errors caused by parasitic capacitance.
2. Description of the Related Art
Sample-and-hold circuits have been used for many years to capture and store an analog voltage sampled at a predetermined point in time. For example, a basic sample-and-hold circuit is described in Integrated Electronics: Analog And Digital Circuits And Systems, by Millman and Halkias, McGraw-Hill Book Company, 1972, pp. 570-571. A basic sample-and-hold circuit includes a mechanical or electronic switch or gate for selectively passing an analog voltage signal, and a storage capacitor in series with the switch for storing the analog voltage that was coupled by the switch to the storage capacitor just before the switch is opened. A practical sample-and-hold circuit also includes an operational amplifier configured in unity-gain feedback mode; the positive high-impedance input terminal of the op amp is coupled to the storage capacitor for receiving the sample voltage, while the negative input terminal of the op amp is connected to the low-impedance output terminal of the op amp. The output terminal of the op amp thereby tracks the sampled voltage, but the storage capacitor is isolated from any load being driven by the output terminal of the op amp.
Such sample-and-hold circuits are often used in integrated circuits used to drive analog voltages onto the columns of a liquid crystal display (LCD). Analog voltages are driven onto the columns of an LCD display in order to apply desired analog voltages to the various pixels of the display to create a desired image. The LCD display pixels are divided into rows and columns to form an array. A first row is selected, and the analog voltages to be applied to the pixels in the first row are driven onto the columns of the display; a second row is then selected, and new analog voltages are driven onto the columns of the display corresponding to the voltages to be applied to the pixels in the second row. This process is repeated for each row of the display. A sample-and-hold circuit is useful in such applications to temporarily store the analog voltage that is to be driven onto a column of the display during a particular row drive cycle.
To increase the speed of such LCD column driving circuitry, it may be desired to look ahead at the next analog voltage that will be applied to a particular column. In other words, the column driver circuit can be provided with a second analog voltage to be displayed on the second row drive cycle even before the column driver circuit has finished driving the first analog voltage onto the LCD display column during the first row drive cycle. In this mode of operation, the sample-and-hold circuitry is essentially buffering incoming analog values one cycle ahead of the cycle during which they are driven onto the columns of the LCD display. Such a circuit is shown in Prior Art FIG. 1, wherein an analog bus 10 is driven by an analog bus driver 12, and wherein a first analog switch 14 selectively couples the analog voltage on the bus to node 15 and to storage capacitor 16 (Cs) when control signal S1 is active; this might represent the analog voltage to be driven onto the LCD column during a second row drive cycle. A second analog switch 18 selectively couples the analog voltage on node 15 and storage capacitor 16 to node 19 and to the positive input terminal 20 of op amp 22 when control signal S2 is active. Note that a second capacitor 24 (Cp) is shown in FIG. 1 between node 19 and ground; this second capacitor 24 represents parasitic capacitance associated with node 19. Assuming switch 18 is open, then node 19 can represent the analog voltage to be driven onto the LCD column during the first row drive cycle, while node 15 is sampling the analog voltage to be driven onto the column during the second row drive cycle.
A problem that arises with the circuitry shown in FIG. 1 is that parasitic capacitance 24, associated with node 19 and the input terminal 20 of op amp 22, steals some of the charge stored on storage capacitor 16. Due to charge conservation, some of the charge that was originally stored on storage capacitor 16 will leak onto parasitic capacitance 24, which will create an error in the analog voltage that is amplified by amplifier 22 and being driven out onto the column of the LCD display. If the magnitude of the parasitic capacitance 24 is Cp, and the magnitude of the storage capacitance of storage capacitor 16 is Cs, then the error voltage is simply the magnitude of the parasitic capacitance Cp divided by the sum of Cp plus Cs, all multiplied by Vdiff, where Vdiff is the voltage difference between the voltage originally saved on storage capacitor 16 and the voltage that was previously charged across the parasitic capacitance 24. The worst case Vdiff (or Vmax) is the full-scale voltage swing of the minimum and maximum analog voltages to be driven onto the LCD column.
Accordingly, it is an object of the present invention to provide a sample-and-hold circuit to temporarily store analog voltages before coupling such analog voltages to an amplifier wherein errors in the sampled analog voltage due to parasitic capacitances are minimized when such voltage is passed to an amplifier for being driven onto the output of the amplifier.
It is a further object of the present invention to provide such a sample-and-hold circuit in a form suitable for use in electronic circuitry used to drive analog voltages onto the columns of an LCD display.
Still another object of the present invention is to provide such a sample-and-hold circuit which minimizes such errors without significantly complicating known sample-and-hold circuit techniques, and without significantly increasing the size of integrated circuits using such improved sample-and-hold circuit.
Yet another object of the present invention is to provide such a sample-and-hold circuit which may be used to reduce the size of integrated circuits that must sample and hold analog voltages while reducing analog voltage offset errors.
These and other objects of the present invention will become more apparent to those of skill in the art as the description of the present invention proceeds.
Briefly described, and in accordance with a preferred embodiment thereof, the present invention relates to a buffered sample-and-hold circuit for sampling an analog voltage and including a first sampling capacitor and a first switch coupled between a source of an analog voltage and the first sampling capacitor. The first switch selectively couples the analog voltage source to the first sampling capacitor. A second switch is interposed between the first sampling capacitor and the input terminal of a unity gain amplifier; this second switch selectively couples the voltage stored on the first sampling capacitor to the input terminal of the unity gain amplifier.
The components described thus far are present in known buffered sample-and-hold circuits. However, the present circuit further includes a second sampling capacitor; in the preferred embodiment of the present invention, this second sampling capacitor has a capacitance that is substantially equal to that of the first sampling capacitor; this second sampling capacitor is selectively coupled to the analog voltage source by a third switch. In addition, a fourth switch is interposed between the second sampling capacitor and the input terminal of the unity gain amplifier for selectively coupling the voltage stored on the second sampling capacitor to the input terminal of the unity gain amplifier.
In operating the circuitry of the present invention, control signals temporarily open the second and fourth switches so that a former analog voltage previously applied to the input terminal of the amplifier is not disturbed by any changes in the analog voltage source. This effectively disconnects the amplifier input from the analog voltage source, and allows the amplifier to continue supplying the former analog voltage. The control signals then allow the first and third switches to close for applying a new analog voltage source across the first and second sampling capacitors, thereby charging the first and second sampling capacitors to the new analog voltage. Preferably, the control signals then cause the first and third switches to open again in order to disconnect the first and second sampling capacitors from the analog voltage source; the analog voltage source can then be updated in preparation for providing the next analog voltage without disturbing the analog voltage stored on the first and second sampling capacitors.
When it is time to transfer the analog voltage stored on the first and second sampling capacitors to the input of the amplifier, the control signals first close the fourth switch, but leave the second switch open, for allowing the second sampling capacitor to pre-charge the input of the amplifier to the sampled analog voltage. For the reasons explained above, there will be some error due to charge sharing between the second sampling capacitor and the parasitic capacitance associated with the input of the amplifier. However, the input of the amplifier, and any parasitic capacitances associated therewith, will charge to very near the desired sampled voltage; in other words, the pre-charged voltage on the input of the amplifier will not differ greatly from the analog voltage that was sampled by the first sampling capacitor.
The fourth switch is then turned off (i.e., opened) by the control signals, and now the third switch is turned on (i.e., closed) to connect the first sampling capacitor to the input of the amplifier. This time, there is very little error on the voltage established at the input of the amplifier because the sampled analog voltage stored on the first sampling capacitor is not very far apart from the pre-charged voltage already applied to the amplifier input by the second sampling capacitor. Accordingly, the error in the analog voltage provided at the output of the amplifier is significantly reduced.
The present invention also relates to the above-described method of operating a buffered sample-and-hold circuit, including the steps of coupling the analog voltage source to be sampled onto the first and second sampling capacitors for storage thereby, temporarily coupling the second sampling capacitor to the input terminal of the amplifier to apply the pre-charged voltage thereto, and thereafter de-coupling the second sampling capacitor from the input terminal of the amplifier, and coupling the first sampling capacitor to the input terminal of the amplifier for establishing the sampled analog voltage at the input terminal of the amplifier. In practicing such method, it is preferred that the second sampling capacitor be selected to have a capacitance substantially equal to that of the first sampling capacitor. Ideally, the first and second sampling capacitors are de-coupled from the analog voltage source before coupling the second sampling capacitor to the input terminal of an amplifier to perform the pre-charge function.